There continues to be an effort in the microelectronics industry to increase the density of circuit features in a way that favors economies of scale. Photolithography has proven to be a very successful technique for manufacturing integrated circuits (ICs) having narrow linewidths, and there is every expectation that it will continue to be useful in the production of ICs at ever higher resolution for at least the next several years.
As part of the IC manufacturing process, metal is deposited onto a substrate, with the metal being etched to form nanoscale size features that define the workings of the IC. One way of laying down metal is to electrolessly deposit it. In conventional methods of forming circuitization by electroless plating onto dielectric materials, a seeding or catalyst layer is first blanket deposited on the substrate. Next, a negative resist (typically a photoresist) is applied over the seed layer, followed by exposing the photoresist to electromagnetic radiation to form a desired image. The photoresist is then exposed to a developer, i.e., a solvent that dissolves the unexposed portions of the photoresist, leaving the exposed portions of the photoresist over the seed layer. (The analogous positive resist processes are also possible.) Those portions of the photoresist that are removed by the developer correspond to the metal pattern of the circuitization for the circuit board. Typically, several processing steps are performed to accelerate the catalyst, modify the seed layer, and so on. Thereafter, metal is electrolessly plated onto the bare, exposed portions of the seed layer, that is, the portions of the seed layer that are not covered by the photoresist. The polymerized photoresist is then stripped using stripping solvents. As a result, portions of the seed layer are covered by metal circuitization, while portions of the seed layer are exposed.
After plating, the exposed portion of the seed layer can be stripped (that is, the portion of the seed layer that is not covered by the electrolessly plated metal). If the entire seed layer were to remain, the metal in the seed layer might conduct current from one electrical line in the circuit to another electrical line, thereby creating a short circuit. If the exposed portions of the seed layer are to be stripped, another processing step is required. Moreover, the solvents needed to remove the seed layer (for example, alkaline cyanide solutions) often present environmental problems, e.g., such as those related to waste disposal. Furthermore, such solvents often attack and degrade the circuitry and the dielectric materials.
There is still a need for a method of forming circuitization by electrolessly plating metal that does not involve a blanket seed layer, that is simple to perform, and that does not require stripping of the seed layer. From a manufacturing standpoint, it would also be advantageous to reduce both the complexity and the number of process steps.